The invention is useful in computer systems, for example the computer system of FIG. 1. The FIG. 1 system includes system bus 1, central processing unit (CPU) 2, pipelined graphics processor (GPU) 4, input device 3, memory 5, frame buffer 6, and display device 8, connected as shown. Display device 8 is typically a liquid crystal (or other flat panel) display or cathode ray tube monitor. GPU 4 is coupled to system bus 1 via host slave interface 10. In response to input data received over the system bus, pipelined processing circuitry 12 in GPU 4 generates video data for display by device 8. Circuitry 12 can include a vertex processor (for generating vertex data indicative of the coordinates of the vertices of each primitive of each image to be rendered and attributes of each vertex), a rasterizer (for generating pixel data in response to the vertex data), and pixel processing circuitry for applying textures to and otherwise processing the pixel data from the rasterizer. The video data output from circuitry 12 are asserted to frame buffer 6. Consecutive frames of the video data are asserted by frame buffer 6 to display device 8.
Control circuitry 15 controls operation of pipelined processing circuitry 17 and other elements of GPU 4, including by setting bits in register 29 which are then asserted to circuitry 17 and/or other elements of GPU 4 via multiplexer 30 (to be described below).
GPU 4 is typically implemented as an integrated circuit (chip), a graphics processing portion of a chip (sometimes referred to as a graphics “core” or “core portion”), or two or more chips. Typically, both GPU 4 and frame buffer 6 are implemented as separate chips of a graphics card. Alternatively, both frame buffer 6 and graphics processor 4 are implemented as elements of a single chip.
As shown, GPU 4 includes microcontroller 14 which is implemented in accordance with the invention to control the timing of power up (and power down) operations by GPU 4 and display device 8. Microcontroller 14 includes program memory 16 (typically implemented as a RAM to be referred to herein as a “sequencer RAM”), instruction execution circuitry 20 (sometimes referred to below as “unit” 20), bypass register 28, multiplexer 30, and other elements to be described below.
Variations on GPU 4 that have conventional design (and do not embody the invention) do not include microcontroller 14 and instead employ conventional hardware and/or software to control the timing and sequencing of power up and power down operations of GPU 4 and optionally also display device 8.
For example, such conventional hardware and software can be an implementation of control circuitry 15 that includes timer circuitry, and with an external programmable controller (e.g., CPU 2), controls the timing and sequencing of power up and power down operations of the GPU and device 8 (implemented as a flat panel display). In such a conventional system, the timer circuitry would respond to external control signals (e.g., a “power on” signal from CPU 2 of FIG. 1) by asserting power up or power down signals for the flat panel display and for internal circuitry in the GPU with selectable delay times determined by the external controller. For example, an external control signal could trigger execution of the following operations in a predetermined sequence: turning the backlight of the flat panel display on or off, causing the flat panel display to start or cease generating a display in response to video data in frame buffer 6, and commencing or ceasing application of power to the flat panel display and internal components of the GPU. However, because the external controller employed (with timer circuitry as described) with a conventional GPU is conventionally a general-purpose processor, the external controller is subject to interrupts and thus cannot provide guaranteed timing.